(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a new and improved method of providing an Electrostatic Discharge (ESD) protection device for the deep sub-micron semiconductor fabrication of Shallow Trench Isolation (STI) regions.
(2) Description of the Prior Art
The continued decrease in semiconductor device feature size, that has been driven by continued efforts in the semiconductor manufacturing industry to improve device performance by reducing device feature size, has made semiconductor devices increasingly vulnerable to Electrostatic Discharge (ESD). ESD can be triggered in a semiconductor device by any unforeseen build up of electromagnetic fields that affect current carrier distribution and existing magnetic fields in the semiconductor device. To prevent this kind of damage an ESD protection circuit is typically included in the design of a semiconductor device. A semiconductor device can for instance also be damaged by a voltage surge that is introduced into the device via a bond pad. This voltage surge can be induced by direct contact with surrounding equipment to which the bond pad is connected or by human contact. The essential function of the ESD protection arrangement is to direct the ESD current away from the circuits that the ESD circuit is designed to protect. ESD circuits are used to protect memory circuits, MOSFET's and other semiconductor device applications for the protection of input/output buffers. Another typical application of ESD circuits relates to the packaging of individual die into multi-chip modules. This latter application typically requires the use of a number of pads that interconnect the individual die into a multi-die package. Furthermore, a single die can be mounted into a test carrier for testing, which also requires the interfacing of the die with the test environment by means of die contact bonds. These contact bonds are subject to introduction of ESD based damage to the device under test leading to the use of ESD circuits for the protection of the semiconductor die. Bond pad leakage in such an arrangement can be between the input and output pads on a die to other pads on the die such as the power pads, ground pads and bias voltage pads. Pad leakage can also occur from a pad to the silicon substrate of a die, or to another component of the die. One cause of pad leakage can be from defective or damaged electrostatic discharge (ESD) circuits formed on the die. Protective ESD circuits are typically located between the input and output pads on the die and the transistor gates to which the pads are electrically connected. The ESD circuits provide in this manner a path of conductance from the input/output pads to a ground pad, or to a power or bias voltage path for the die. This electrical path is designed to be triggered by a high voltage, which is higher than the operating voltage, so that the current can be discharged at a rapid rate once an electrostatic discharge takes place through the input or output pads of the die. Where the ESD circuits are defective or inoperable, the current that is applied to an input or output pad can leak from these pads through the ESD circuit to other pads on the die or to the substrate.
Arrangements of ESD protection circuits are used whereby more than one of these ESD circuits surrounds a bond pad. Typically, an ESD protection circuit will consist of a circuit configuration that contains a resistor, a capacitor and a inductance (or reactance). Some ESD protection circuits may include a primary and a secondary protection circuit. Key to the successful operation of an ESD circuit configuration is that these circuits individually or collectively react fast enough so that any surge in current can be interrupted or deflected in time to protect the surrounding circuits from damage. In order to achieve this objective ESD protection circuits frequently use highly sensitive thin (for instance oxide) films or a transistor design that, by for instance using a thin-film gate oxide layer between the gate electrode and the underlying substrate, will rapidly react to improperly applied voltages and will as a consequence interrupt their normal operation and serve as a protective circuit. It is clear that by careful selection of the various design parameters of such circuits, these ESD protection circuits can be made to operate in a collective manner and in a manner that is sensitive to the level of induced voltages. A primary protection circuit can for instance be electrically isolated (by a resistive load) from the secondary protection circuit such that the interrupting capabilities (determined by for instance the thickness of the oxide layer underlying the gate electrode of the secondary circuit or by the size of the drain structure of this circuit) of the gate electrode can be optimized. These latter observations point to the conventional design approach for the ESD protective circuit of using the design of the drain regions of a gate electrode or the length of the source/drain region (the channel) underlying the gate electrode as the design parameters.
In a typical design of memory circuits, the ESD protection circuit is located adjacent to and in close physical proximity with the memory circuits that may include memory cell arrays and peripheral circuits. The peripheral circuits include NMOS and PMOS transistors. The active regions of the memory circuits are electrically isolated by forming non-active regions between these circuits, these non-active regions are also referred to as field oxide regions and can be formed using any of the conventional approaches such as with the Local Oxidation of Silicon (LOCOS) process or by forming Shallow Trench Isolation (STI) regions. After the surface of the substrate has been defined in this manner (defining the region for the ESD circuit and for the memory circuits whereby the active ESD and memory circuits are electrically separated by field isolation regions), a layer of field oxide is grown over the surface of the substrate. The polarity of the transistors that are to be formed is defined by implanting n-type and p-type impurities in the surface of the substrate thereby defining n-wells and p-wells regions in the substrate. These impurity implants are performed in a sequence of steps using appropriate masking and impurity types and implant energies such that the required conductivity of the transistors that are required (ESD protective circuit, NMOS and PMOS transistor, others) and their supporting regions (source/drain) are provided.
FIG. 1 shows a cross section of a Prior Art ESD protection device that has been created on the surface of a semiconductor substrate 10. The Prior Art cross section that is shown in FIG. 1 is a metal gate field threshold device and contains a layer 14 of field oxide, a source region 12 and a drain region 13 that are adjacent to the field oxide layer 14, a threshold voltage adjustment region 16 underlying the field oxide layer 14, a layer 18 of gate oxide and two metal contacts 20 and 22 that respectively contact the source (12) and drain (13) regions of the ESD protection circuit.
A layer 16 of P-type dopant is typically implanted in substrate 10 under the layer 14 of field oxide. The implant is performed in order to increase the field isolation of the metal gate field threshold device. Due to this implant, the threshold voltage of the device can be raised to in excess of 12 volts. Typical gate widths have been reduced to the point where 0.35 um gate width is applied. With this sharp reduction in gate width comes an equally sharp reduction in the thickness of the gate oxide layer. The gate oxide layer 18 that can be used with a gate width of 0.35 um is between about 60 and 80 Angstrom thick. The breakdown voltage of this layer of gate oxide is about 8 volts. With the reduction in the gate size, the width of the source/drain depletion layer is correspondingly reduced and can approach the channel length of the gate electrode. This readily leads to punch through between the source and the drain whereby the depletion layers of the source and the drain regions touch and the required current control by the gate electrode between the source and the drain is no longer effective. Where, on the other hand, a deep trench is used for the STI region, that is trench 14 in FIG. 1, a thick oxide layer is used for the ESD protection circuit. The trench that is indicated in FIG. 1 is about 3500 Angstrom thick, the layer of oxide is between 100 and 400 Angstrom thick. The invention addresses this application and the use of a very high energy implant that is used to establish a deep enough junction for deep STI trenches. The invention shows an ESD protection device that is entirely over the STI region and that in not over any active region of the device.
U.S. Pat. No. 5,629,544 (Voldman et al.) shows an ESD gate at least partially over an STI region. See FIG. 4A; see cols. 3 and 4.
U.S. Pat. No. 5,744,841 (Gilbert) shows an ESD over a FOX.
U.S. Pat. No. 5,918,117 (Yum) shows an ESD device using STI 42. See col.5, line 43 and col. 7.
U.S. Pat. No. 5,489,792 (Hu et al.) teaches an ESD over a SOI.
U.S. Pat. No. 5,885,875 (Hsu) shows an ESD gate over a fox.